* Update documentation to include the changes done
for supporting more than one SDO lane.
* Update the register map;
* Insert SDI/SDO lane mask registers;
* Update Configuration Write Instruction;
* Update parameter from NUM_OF_SDI to NUM_OF_SDIO.

Signed-off-by: Carlos Souza <[email protected]>

There is a different register for SDI lane mask and SDO
lane mask;
Update the NUM_OF_SDI parameter to NUM_OF_SDIO parameter to reflect
that both SDI and SDO are symmetrical. The control over them is
through the SDI/SDO lane masks.

Inserts a ready signal for when the valid_indices
has finished its inner logic. This avoid the possible
issue where the latency of the command is smaller than
this logic. This could only happen in the FIFO mode.

Signed-off-by: Carlos Souza <[email protected]>

Update NUM_OF_SDI to NUM_OF_SDIO in the projects documentations.
The variable was updated on the spi_engine library since SDI and
SDO have symmetrical sizes.

Signed-off-by: Carlos Souza <[email protected]>

Updated the projects to use NUM_OF_SDIO parameter. It is the same
project, no functionality has changed.

Signed-off-by: Carlos Souza <[email protected]>

fix DATA_WIDTH register.

Signed-off-by: Carlos Souza <[email protected]>

It was missing the sdi_lane_mask register.
That was not affecting execution because the only
logic requiring this register is on the axi_spi_engine.v

Signed-off-by: Carlos Souza <[email protected]>

Signed-off-by: Laez Barbosa <[email protected]>

Previous code would create issues for lane masks different from
ALL_ACTIVE_LANE_MASK, due to a pipelining bug. Although the currently officially
supported behavior is only either one lane active or all lanes active, this is a
very simple change that helps us prepare in case we want to support other lanes
in the future, and removes some extra logic (a comparison and a mux), which can
improve timing.

Signed-off-by: Laez Barbosa <[email protected]>

Signed-off-by: Laez Barbosa <[email protected]>

Introduces logic to keep track of the number of elements in
the SDI FIFO. This is due to the asymmetric FIFO implementation
not including the logic for this, and instead outputting the
level of one of its internal FIFOs.

Signed-off-by: Laez Barbosa <[email protected]>

Signed-off-by: Laez Barbosa <[email protected]>

Fixes the bug related to the sdo lane config instruction, which
was high all the time and not for a single cycle. That was causing
the data_assemble module to be rebuilding the lookup table, and
consequently affecting the output of the offload mode.

Removed lane_index_d because it is not necessary anymore. Both FIFO
and OFFLOAD modes are using the valid_indices lookup table.

Signed-off-by: Carlos Souza <[email protected]>

The modifications performed in this library are not backwards compatible. So
this version is Spi Engine 2.0.

Signed-off-by: Carlos Souza <[email protected]>

Cosmetic changes and fixed ad463x project that had some issues after the
rebase.

Signed-off-by: Carlos Souza <[email protected]>

Fix g_sdo_shift_reg for that did not have a generate block. Also
improves timing for the spi_engine_execution_shiftreg_data_assemble
module, which was necessary for working on the quartus version of the
AD4052 project.

Signed-off-by: Carlos Souza <[email protected]>

Update scripts for generating the spi engine for quartus projects. Also
updated Makefile that had a missing fifo asym library for quartus.

Signed-off-by: Carlos Souza <[email protected]>

Fixes quartus scripts for ad4052 in quartus. Also adds optimization
options for timing closure of the project.
Removes wrong timing constraints for the coraz7s.

Signed-off-by: Carlos Souza <[email protected]>

Fixes almost full threshold parameter in fifo asym. Updated to 31,
as it was previously implementation.

Signed-off-by: Carlos Souza <[email protected]>